基于FPGA的频率计与串口通信（二）
接上篇，本文章展示基于FPGA的频率计与串口通信项目部分核心代码。
顶层文件
top.bdf
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(pin
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(pin
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(pin
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(parameter
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"0000000101000101"
""
(type "PARAMETER_UNSIGNED_BIN") )
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(junction (pt 280 336))该文件为工程的顶层文件，相当于C语言中的主函数，下面的文件相当C语言中的子函数。
频率采集模块
test_f.v
module text_f(
sysclk,
inclk,
outclk,
seg_duan,
seg_wei,
start,
send_finish,
key,
count1,
count2,
count3,
count4,
count5,
count6,
count7,
count8
);
input sysclk,inclk;//系统时钟
output outclk;
output start;
input send_finish;
input key;
output [7:0] seg_duan,seg_wei;//输入时钟
output [7:0] count1;
output [7:0] count2;
output [7:0] count3;
output [7:0] count4;
output [7:0] count5;
output [7:0] count6;
output [7:0] count7;
output [7:0] count8;
wire sysclk,inclk;//系统时钟//输入时钟
reg start;
reg [24:0] clk_counter;//时钟计数
reg clk_div;//分频后的时钟
reg [7:0] seg_duan,seg_wei;//输入时钟
reg [7:0] data;
reg [3:0] counter1,counter2,counter3,counter4,counter5,counter6,counter7,counter8;
reg [7:0] count1,count2,count3,count4,count5,count6,count7,count8;
reg [3:0] count1_seg,count2_seg,count3_seg,count4_seg,count5_seg,count6_seg,count7_seg,count8_seg;
reg [14:0] counter1_clk;
reg [15:0] counter2_clk;
reg test_clk1;
reg test_clk2;
reg outclk;
/***********************产生测试时钟1**************************************/
always @(posedge sysclk)
begin
if(counter1_clk == 15'b110_0001_1010_1000)
begin
test_clk1<=~test_clk1;//500HZ
counter1_clk<=15'b0;
end
else
counter1_clk<=counter1_clk+1'b1;
end
/***********************产生测试时钟2**************************************/
always @(posedge sysclk)
begin
if(counter2_clk == 16'd50000)
begin
test_clk2<=~test_clk2;//250HZ
counter2_clk<=16'b0;
end
else
counter2_clk<=counter2_clk+1'b1;
end
/***********************选择输出的时钟**************************************/
always @(key)
begin
if(key == 1'b1)
outclk <= test_clk1;
else
outclk <= test_clk2;
end
/**********************产生1HZ的时钟************************************/
always @(posedge sysclk)
begin
if(clk_counter==25'b1_0111_1101_0111_1000_0100_0000)
begin
clk_div<=~clk_div;
clk_counter<=25'b0;
end
else
clk_counter<=clk_counter+1'b1;
end
/*********************测试待测信号***********************************/
always @(posedge outclk)
begin
if(clk_div)
begin
start <= 1'b0;
if(counter1==4'b1001)
begin
counter1<=4'b0;
counter2<=counter2+1'b1;
if(counter2==4'b1001)
begin
counter2<=4'b0;
counter3<=counter3+1'b1;
if(counter3==4'b1001)
begin
counter3<=4'b0;
counter4<=counter4+1'b1;
if(counter4==4'b1001)
begin
counter4<=4'b0;
counter5<=counter5+1'b1;
if(counter5==4'b1001)
begin
counter5<=4'b0;
counter6<=counter6+1'b1;
if(counter6==4'b1001)
begin
counter6<=4'b0;
counter7<=counter7+1'b1;
if(counter7==4'b1001)
begin
counter7<=4'b0;
counter8<=counter8+1'b1;
if(counter8==4'b1001)
begin
counter8<=4'b0;
end
end
end
end
end
end
end
end
else
counter1<=counter1+1'b1;
end
else
/*******************测试结果寄存********************************/
begin
start <= 1'b1;
if(counter1!=4'b0000|counter2!=4'b0000!=4'b0000|counter3!=4'b0000|counter4!=4'b0000|
counter5!=4'b0000|counter6!=4'b0000|counter7!=4'b0000|counter8!=4'b0000)
begin
count1<=counter1+8'd48;
count2<=counter2+8'd48;
count3<=counter3+8'd48;
count4<=counter4+8'd48;
count5<=counter5+8'd48;
count6<=counter6+8'd48;
count7<=counter7+8'd48;
count8<=counter8+8'd48;
count1_seg<=counter1;
count2_seg<=counter2;
count3_seg<=counter3;
count4_seg<=counter4;
count5_seg<=counter5;
count6_seg<=counter6;
count7_seg<=counter7;
count8_seg<=counter8;
counter1<=4'b0000;
counter2<=4'b0000;
counter3<=4'b0000;
counter4<=4'b0000;
counter5<=4'b0000;
counter6<=4'b0000;
counter7<=4'b0000;
counter8<=4'b0000;
end
end
end
/*****************测试结果数码管显示*************************/
always @(clk_counter , count1_seg , count2_seg , count3_seg , count4_seg , count5_seg , count6_seg , count7_seg , count8_seg,data)
begin
case(clk_counter[15:13])//数码管位扫描
3'b000:begin seg_wei<=8'b1111_1110;data<=count1_seg;end
3'b001:begin seg_wei<=8'b1111_1101;data<=count2_seg;end
3'b010:begin seg_wei<=8'b1111_1011;data<=count3_seg;end
3'b011:begin seg_wei<=8'b1111_0111;data<=count4_seg;end
default:begin seg_wei<=8'bx;data<=4'bx;end
endcase
case(data[3:0])//数码管显示
4'b0000:begin seg_duan<=8'b1100_0000;end//0
4'b0001:begin seg_duan<=8'b1111_1001;end//1
4'b0010:begin seg_duan<=8'b1010_0100;end//2
4'b0011:begin seg_duan<=8'b1011_0000;end//3
4'b0100:begin seg_duan<=8'b1001_1001;end//4
default:seg_duan<=8'bx;
endcase
end
endmodule串口模块
uart.v
//串口通信__FPGA和上位机通信(波特率：9600bps,10个bit是1位起始位，8个数据位，1个结束)
module uart(
clk,
rst,
rxd,
txd,
start,
data_cnt,
count1,
count2,
count3,
count4,
count5,
count6,
count7,
count8,
send_finish
);
input clk; //系统50MHZ时钟
input rst; //复位
input rxd; //串行数据接收端
output txd; //串行数据发送端
input start; //开始采集信号
input[3:0] data_cnt; //数据位标志
output send_finish; //发送完成标志
input [7:0] count1;
input [7:0] count2;
input [7:0] count3;
input [7:0] count4;
input [7:0] count5;
input [7:0] count6;
input [7:0] count7;
input [7:0] count8;
reg[15:0] div_reg; //分频计数器，分频值由波特率决定。分频后得到频率8倍波特率的时钟
reg[2:0] div8_tras_reg; //该寄存器的计数值对应发送时当前位于的时隙数
reg[3:0] state_tras; //发送状态寄存器
reg clkbaud_tras; //以波特率为频率的发送使能信号
reg clkbaud8x; //以8倍波特率为频率的时钟，它的作用是将发送或接受一个bit的时钟周期分为8个时隙
reg trasstart; //开始发送标志
reg send_finish;
reg txd_reg; //发送寄存器
reg[7:0] rxd_buf; //接受数据缓存
reg[7:0] txd_buf; //发送数据缓存
reg[3:0] send_state; //发送状态寄存器
parameter div_par=16'h145;
//分频参数，其值由对应的波特率计算而得，按此参数分频的时钟频率是波倍特率的8
//倍，此处值对应9600的波特率，即分频出的时钟频率是9600*8 (CLK50M)
assign txd = txd_reg;
// assign send_state=data_cnt;
/*******分频得到8倍波特率的时钟*********/
always@(posedge clk )
begin
if(!rst)
div_reg<=0;
else begin
if(div_reg==div_par-1'b1)
div_reg<=0;
else
div_reg<=div_reg+1'b1;
end
end
always@(posedge clk)
begin
if(!rst)
clkbaud8x<=0;
else if(div_reg==div_par-1'b1)
clkbaud8x<=~clkbaud8x;//分频得到8倍波特率的时钟:clkbaud8x
end
// *******************************/
always@(posedge clkbaud8x or negedge rst)//clkbaud8x
begin
if(!rst)
div8_tras_reg<=0;
else if(trasstart)
div8_tras_reg<=div8_tras_reg+1'b1;//发送开始后，时隙数在8倍波特率的时钟下加1循环
end
always@(div8_tras_reg)
begin
if(div8_tras_reg==7)
clkbaud_tras=1;//在第7个时隙，发送使能信号有效，将数据发出
else
clkbaud_tras=0;
end
// *********发送数据模块***************/
always@(posedge clkbaud8x or negedge rst)//clkbaud8x
begin
if(!rst)
begin
txd_reg<=1;//发送寄存器置高
trasstart<=0;//开始发送标志置低
txd_buf<=8'h00;//发送缓存器清零
state_tras<=0;//发送状态寄存器清零
send_finish <= 1'b0;
send_state<=4'd0;
end
else
if(start == 1'b1)
case(state_tras)
4'b0000: begin //发送起始位
send_finish <= 1'b0;
if(!trasstart&&send_state<4'd9)
trasstart<=1;
else if(send_state<4'd9) begin
if(clkbaud_tras) begin
txd_reg<=0;
state_tras<=state_tras+1'b1;
end
end
else begin
state_tras<=0;
end
end
4'b0001: begin //发送第1位
if(clkbaud_tras) begin
txd_reg<=txd_buf[0];
txd_buf[6:0]<=txd_buf[7:1];
state_tras<=state_tras+1'b1;
end
end
4'b0010: begin //发送第2位
if(clkbaud_tras) begin
txd_reg<=txd_buf[0];
txd_buf[6:0]<=txd_buf[7:1];
state_tras<=state_tras+1'b1;
end
end
4'b0011: begin //发送第3位
if(clkbaud_tras) begin
txd_reg<=txd_buf[0];
txd_buf[6:0]<=txd_buf[7:1];
state_tras<=state_tras+1'b1;
end
end
4'b0100: begin //发送第4位
if(clkbaud_tras) begin
txd_reg<=txd_buf[0];
txd_buf[6:0]<=txd_buf[7:1];
state_tras<=state_tras+1'b1;
end
end
4'b0101: begin //发送第5位
if(clkbaud_tras) begin
txd_reg<=txd_buf[0];
txd_buf[6:0]<=txd_buf[7:1];
state_tras<=state_tras+1'b1;
end
end
4'b0110: begin //发送第6位
if(clkbaud_tras) begin
txd_reg<=txd_buf[0];
txd_buf[6:0]<=txd_buf[7:1];
state_tras<=state_tras+1'b1;
end
end
4'b0111: begin //发送第7位
if(clkbaud_tras) begin
txd_reg<=txd_buf[0];
txd_buf[6:0]<=txd_buf[7:1];
state_tras<=state_tras+1'b1;
end
end
4'b1000: begin //发送第8位
if(clkbaud_tras) begin
txd_reg<=txd_buf[0];
txd_buf[6:0]<=txd_buf[7:1];
state_tras<=state_tras+1'b1;
end
end
4'b1001: begin //发送停止位
if(clkbaud_tras) begin
txd_reg<=1;
txd_buf<=8'h00;
state_tras<=state_tras+1'b1;
end
end
4'b1111:begin
if(clkbaud_tras) begin
state_tras<=state_tras+1'b1;
send_state<=send_state+1'b1;
trasstart<=0;
case(send_state)
4'b0000:
txd_buf<=count8;//
4'b0001:
txd_buf<=count7;//
4'b0010:
txd_buf<=count6;//
4'b0011:
txd_buf<=count5;//
4'b1000:
begin
txd_buf<=8'd10;//换行符
send_finish <= 1'b1;
send_state<=4'b0000;
end
default:
txd_buf<=8'd0;
endcase
end
end
default: begin
if(clkbaud_tras) begin
state_tras<=state_tras+1'b1;
trasstart<=1;
end
end
endcase
end
endmodule原文地址：https://blog.csdn.net/m0_45161011/article/details/138045869
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